FPGA & Reconfigurable Computing
Custom logic where a CPU will not do.
FPGA design and hardware/software co-design for cases where timing, throughput or determinism rule out a general-purpose processor. Includes partial reconfiguration, where the fabric changes function at runtime rather than being fixed at build time.
Typical engagements
- Board and FPGA bring-up, from first configuration to working data path
- Partial reconfiguration so one device serves several workloads
- High-speed data capture and streaming pipelines
- Register map design, and verification that doc, RTL and software agree
- Timing closure on a design that will not meet constraints
Proof
Work that demonstrates this capability in practice.